Abstract
With the increased usage of SiC and GaN devices in power converters, it is apparent to engineers that the benefits of these devices for low switching losses have to be balanced against two deterrents: (1) the faster rise and fall times of these devices lead to increased harmonic content, making it more difficult to meet Electromagnetic Compatibility (EMC) regulations; and (2) increased sensitivity to parasitic elements in the board layout, leading to higher dv DS /dt and di D /dt with higher current and voltage peak stresses. "Active" gate drives are thus needed to regulate different regions of switching to achieve the optimal tradeoff between switching loss and EMC. We present a simple analog circuit architecture for an active gate drive. Turn on and turn off tests with SiC modules and discrete parts are discussed with experimental results.
