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Integer Sum Reduction with OpenMP on an AMD MI100 GPU...

by Zheming Jin, Jeffrey S Vetter
Publication Type
Conference Paper
Book Title
2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
Publication Date
Page Numbers
496 to 499
Publisher Location
New Jersey, United States of America
Conference Name
36th IEEE International Parallel and Distributed Processing Symposium (IPDPSW)
Conference Location
Lyon, France
Conference Sponsor
IEEE
Conference Date
-

Sum reduction is a primitive operation in parallel computing. Device offload support allows a user to use OpenMP directives to take advantage of a highly capable GPU. In this paper, we present the integer sum reduction annotated with the OpenMP directives and evaluate the performance impacts of tunable parameters with the AOMP and GCC compilers on an AMD MI100 GPU. In addition, we explain the implementations of the OpenMP reduction by the compilers. Sweeping over the pruned parameter space, we find that the speedup is approximately 20 with AOMP, and the reduction performance using AOMP is approximately 11% higher than that using GCC. However, the OpenMP offload performance is approximately 30% lower compared to the performance of the reductions written with rocThrust or hipCUB.