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LastingNVCache: A Technique for Improving the Lifetime of Non-volatile Caches...

by Sparsh Mittal, Jeffrey S Vetter, Dong Li
Publication Type
Conference Paper
Publication Date
Page Numbers
535 to 541
Conference Name
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Conference Location
Tampa, Florida, United States of America
Conference Sponsor
IEEE
Conference Date
-

Use of NVM (Non-volatile memory) devices such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches holds the promise of providing a high-density, low-leakage alternative to SRAM. However, low write endurance of NVMs, along with the write-variation introduced by existing cache management schemes may significantly limit the lifetime of NVM caches. We present LastingNVCache, a technique for improving lifetime of NVM caches by mitigating the intra-set write variation. LastingNVCache works on the key idea that by periodically flushing a frequently-written data-item, the next time the block can be made to load into a cold block in the set. Through this, the future writes to that data-item can be redirected from a hot block to a cold block, which leads to improvement in the cache lifetime. Microarchitectural simulations have shown that LastingNVCache provides 6.36X, 9.79X, and 10.94X improvement in lifetime for single, dual and quad-core systems. Also, its implementation overhead is small and it outperforms a recently proposed technique for improving lifetime of NVM caches.