Abstract
Using high voltage (HV) silicon carbide (SiC) power semiconductors in a modular multilevel converter (MMC) is promising because it results in fewer submodules and lower switching loss compared to conventional Si based solutions. The nearest level pulsewidth modulation (NL-PWM) is commonly used in the MMC for medium voltage applications. However, with the NL-PWM and existing voltage balancing control, there are many submodules that switch their modes in a control cycle, resulting in a high dv/dt during the deadtime of the power semiconductor, which could be multiple times of the dv/dt of the single device. This poses great challenges on the noise immunity and insulation design in the MMC using HV SiC devices, which have very fast switching speed. A novel voltage balancing control, which ensures only two submodules switch their modes in a control cycle, is proposed in this article, limiting the maximum dv/dt to the dv/dt of a single power semiconductor and also maintaining the voltage balance performance. The proposed voltage balancing control is experimentally validated in a 10-kV SiC mosfet based MMC with four submodules per arm.
