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Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study

Publication Type
Conference Paper
Book Title
ICS '24: Proceedings of the 38th ACM International Conference on Supercomputing
Publication Date
Page Numbers
188 to 200
Publisher Location
New York, New York, United States of America
Conference Name
ICS 2024: ACM International Conference on Supercomputing
Conference Location
Kyoto, Japan
Conference Sponsor
ACM, SIGARCH
Conference Date
-

GPU memory corruption and in particular double-bit errors (DBEs) remain one of the least understood aspects of HPC system reliability. Albeit rare, their occurrences always lead to job termination and can potentially cost thousands of node-hours, either from wasted computations or as the overhead from regular checkpointing needed to minimize the losses. As supercomputers and their components simultaneously grow in scale, density, failure rates, and environmental footprint, the efficiency of HPC operations becomes both an imperative and a challenge.

We examine DBEs using system telemetry data and logs collected from the Summit supercomputer, equipped with 27,648 Tesla V100 GPUs with 2nd-generation high-bandwidth memory (HBM2). Using exploratory data analysis and statistical learning, we extract several insights about memory reliability in such GPUs. We find that GPUs with prior DBE occurrences are prone to experience them again due to otherwise harmless factors, correlate this phenomenon with GPU placement, and suggest manufacturing variability as a factor. On the general population of GPUs, we link DBEs to short- and long-term high power consumption modes while finding no significant correlation with higher temperatures. We also show that the workload type can be a factor in memory’s propensity to corruption.