Bio
Narasinga Rao joined ORNL as a software engineer in the Future Technology Group (FTG) in 2019. Narasinga Rao holds the position of a Senior R&D Staff and Group Leader for the Architecture and Performance Group in the Computer Science and Mathematics Division. His current research is on heterogeneous computing, FPGA acceleration, Neuromorphic computing (Spiking Neural Network accelerators) and RISC-V based accelerators. Prior to this, he has worked in Samsung R&D Institute Bangalore (SRIB) for ~8 years on fixed point deep learning inference framework, Samsung Reconfigurable Processors development toolchain (compiler, cycle accurate simulators, etc.) and architecture exploration.
Narasinga received Ph.D. from K.U.Leuven and IMEC R&D (Belgium) in 2012 and M.Tech in Computer Science and Engineering from Indian Institute of Technology Delhi (IIT-D, India).
Professional Experience
- Heterogeneous runtime system (IRIS)
- Heterogeneous Math kernel library (IRIS-BLAS / MatRIS)
- RISC-V based Spiking Neural Network accelerator
- Adrastea: Framework for enabling ML for edge computing using FPGA
- FPGA Development using High Level Synthesis (Xilinx)
- Deep Neural Network Software frameworks and Hardware Accelerators
- GEM5 Simulator
- RISC-V based heterogeneous accelerators (Ranger)
- Reconfigurable Processor Development tools (Compiler and cycle-accurate Simulator)
Awards
* IEEE Senior Member
Education
- Ph.D. from IMEC and K.U.Leuven, Belgium (2012)
- M.Tech from Indian Institute of Technology (IIT)-Delhi (2004)
- B.Tech from Jawaharlal Nehru Technological University (JNTU) Hyderabad (2002)
Professional Service
- ~4 years of experience in ORNL, USA
- ~8 years of experience in Samsung R&D, Bengaluru, India
- ~5 years of experience in IMEC R&D, Belgium
- ~2 years of experience in Agere Systems, India
Professional Affiliations
IEEE Senior Member
Trademarks and Patents
- Miniskar, N.R., Pasupuleti, S.K., Gadde, R.N., Vishnoi, A., Rajagopal, V. and Ramasamy, C.K., Samsung Electronics Co Ltd, 2023. Method and apparatus for determining memory requirement in a network. U.S. Patent 11,593,644. (Granted)
- Miniskar, Narasinga Rao, Frank Y. Liu, and Jeffrey S. Vetter. "Circular queue management with split indexes." U.S. Patent Application 17/500,851, filed April 28, 2022. (Granted)
- Miniskar, N.R., Liu, F.Y., Young, A.R., Vetter, J.S. and Chakraborty, D., UT Battelle LLC, 2022. Hierarchical task scheduling for accelerators. U.S. Patent Application 17/542,022. (Published)
Other Publications
- IRIS-DMEM: An Efficient Memory Management for Heterogeneous Computing. Narasinga Rao Miniskar, Mohammad Alaul Haque Monil, Pedro Valero-Lara, Frank Y. Liu, Jeffrey S. Vetter, IEEE-High Performance Extreme Computing (HPEC) (2023) Outstanding Paper Award
- On-Sensor Data Filtering using Neuromorphic Computing for High Energy Physics Experiments. Kulkarni, Shruti R., Aaron Young, Narasinga Rao Miniskar, Jeffrey S. Vetter, Farah Fahim, Benjamin Parpillon, Jennet Dickinson et al. ICONS (2023).
- A 3D Implementation of Convolutional Neural Network for Fast Inference. Narasinga Rao Miniskar, Pruek Vanna-iampikul, Aaron Young, Sung Kyu Lim, Frank Liu, Jieun Yoo, Corrinne Mills, Farah Fahim, Jeffrey S Vetter. IEEE International Symposium on Circuits and Systems (ISCAS) 2023 May.
- Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials. Vetter, Jeffrey S., Prasanna Date, Farah Fahim, Shruti R. Kulkarni, Petro Maksymovych, A. Alec Talin, Marc Gonzalez Tallada et al. The International Journal of High Performance Computing Applications (2023).
- Tiling Framework for Heterogeneous Computing of Matrix-Based Tiled Algorithms. Narasinga Rao Miniskar, Mohammad Alaul Haque Monil, Pedro Valero-Lara, Frank Liu, Jeffrey S. Vetter. In Proceedings of The International Workshop on Extreme Heterogeneity Solutions (PPOPP ExHET Workshop’23). 2023.
- A survey on processing-in-memory techniques: Advances and challenges. Asifuzzaman, Kazi, Narasinga Rao Miniskar, Aaron R. Young, Frank Liu, and Jeffrey S. Vetter. Journal Memories-Materials, Devices, Circuits and Systems (2023), Elsevier publisher, Volume 4.
- IRIS-BLAS: Towards a Performance Portable and Heterogeneous BLAS Library, Narasinga Rao Miniskar, Mohammad Alaul Haque, Pedro Valero-Lara, Frank Y. Liu, Jeffrey S. Vetter. 29th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC) 2022.
- LaRIS: Targeting Portability and Productivity for LAPACK Codes on Extreme Heterogeneous Systems by Using IRIS. Monil, Mohammad Alaul Haque, Narasinga Rao Miniskar, Frank Y. Liu, Jeffrey S. Vetter, and Pedro Valero-Lara. In 2022 IEEE/ACM Redefining Scalability for Diversely Heterogeneous Architectures Workshop (RSDHA), pp. 12-21. IEEE, 2022.
- Ultra low latency machine learning for scientific edge applications. Miniskar, Narasinga Rao, Aaron Young, Frank Liu, Willem Blokland, Anthony Cabrera, and Jeffrey Vetter. 32nd International Conference on Field Programmable Logic and Applications hosted by Queens University Belfast, UK, 2022.
- Adrastea: An Efficient FPGA Design Environment for Heterogeneous Scientific Computing and Machine Learning. Young, A.R., Miniskar, N.R., Liu, F., Blokland, W., Vetter, J.S. (2022). In: Doug, K., Al, G., Pophale, S., Liu, H., Parete-Koon, S. (eds) Accelerating Science and Engineering Discoveries Through Integrated Research Infrastructure for Experiment, Big Data, Modeling and Simulation. SMC 2022. Communications in Computer and Information Science, vol 1690. Springer, Cham.
- Toward Performance Portable Programming for Heterogeneous Systems on a Chip: A Case Study with Qualcomm Snapdragon SoC. Cabrera, Anthony, Seth Hitefield, Jungwon Kim, Seyong Lee, Narasinga Rao Miniskar, and Jeffrey S. Vetter. In 2021 IEEE High Performance Extreme Computing Conference (HPEC)
- A Hierarchical Task Scheduler for Heterogeneous Computing, Narasinga Rao Miniskar, Frank Liu, Aaron Young, Dwaipayan Chakraborty, Jeffey Vetter, ISC-HPC 2021
- Memory efficient lock-free circular queue, Narasinga Rao Miniskar, Frank Liu, Jeffrey S. Vetter. IEEE International Symposium on Circuits and Systems (ISCAS) 2021 May, 26
- Deffe: a data-efficient framework for performance characterization in domain-specific computing. Frank Liu, Narasinga Rao Miniskar, Dwaipayan Chakraborty, and Jeffrey S. Vetter. 2020. In Proceedings of the 17th ACM International Conference on Computing Frontiers (CF ’20). ACM NY 182–191.